1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device capable of improving reduction of refresh characteristics due to a decrease of design rule.
2. Description of the Prior Art
As generally known in the art, a DRAM (Dynamic Random Access Memory) device belongs to a memory device that can read out stored data if required, is composed of DRAM cells, and includes a MOS transistor acting as a switch and a capacitor storing data, i.e., electrical charges.
With regard to a DRAM device, data storage refers to an accumulation of electrical charges in the capacitor, and the electrical charges accumulated in the capacitor ideally do not vanish. However, initial electrical charges stored in the capacitor may vanish due to leakage currents produced in a p-n junction, etc., of the MOS transistor, thereby producing a natural loss of data.
Accordingly, it is required to recharge the DRAM device to an amount of initial electrical charge, corresponding to the readout information after reading out the stored data, prior to the complete vanishing of the stored data in the respective DRAM cells. This recharging process of the electrical charges stored in cells is referred to as a refresh action, and data storage in the respective DRAM cells can be maintained by the periodical repetition of the refresh action.
In this procedure, the period of the refresh action closely relates to a forming process of a capacitor, and it is controlled by ion implantation after the formation of a storage node contact in the general fabrication process of the DRAM. That is, with regard to a conventional DRAM device, impurities are implanted into an exposed source/drain region in order to improve the refresh characteristics, i.e., to reduce the electric field in the junction region.
However, a high channel doping with a concentration below about 2.0E13/cm2 is required to control a threshold voltage of a sub-cell transistor having a size of 0.15 xcexcm following the decrease of the design rule. Here, the concentration of a LDD (low doped drain) region increases to produce the serious increase of the electrical field in the junction region, and as a result, the refresh time remarkably decreases due to the increase of the abnormal junction leakage originated from a trap assisted tunneling.
Meanwhile, in the conventional art, ion implantation is additionally performed to control the threshold voltage of a channel by masking the storage node part, i.e., the junction part in contact with the capacitor to improve the decrease of the refresh time. At this time, the refresh time and the threshold voltage vary drastically because of the misalignment during the ion implantation of the threshold voltage region and the formation of the gate.
As described above, there has been a limitation in achieving an electrical field mitigation in the junction region with a conventional DRAM fabrication process, following the decrease of the design rule, and it has been difficult to secure refresh characteristics.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for fabricating a semiconductor device capable of improving a refresh characteristics.
In order to accomplish this object, there is provided a method for fabricating a semiconductor device, comprising the steps of: performing a first ion implantation into the semiconductor substrate to control the threshold voltage Vt, forming a gate electrode on the semiconductor substrate in which a first ion implantation having been performed, performing a second ion implantation using the gate electrode as a mask with a tilt of desired degree in order to control the threshold voltage, and performing a third ion implantation to form an LDD region in the substrate region at both sides of the gate electrode.
In the method of the present invention, the first ion implantation is performed at a concentration range of below 90% of the whole doping concentration required to control the threshold voltage, and the second ion implantation is performed at an angle of less than 30xc2x0, and at two directions or four directions vertical to the gate electrode.